1. Field of the Invention
The present invention relates to an integrated circuit comprising MOS-type transistors.
2. Description of the Related Art
The technological progress of methods for manufacturing integrated circuits and in particular circuits comprising MOS-type transistors generally goes along with a decrease in the surface area taken up by each transistor. The drain, source, and channel surface areas, as well as the gate oxide thickness, are decreased. This geometric decrease generally goes along with a decrease in the bias voltage of the integrated circuit components. However, the bias voltage of transistors decreases proportionally slower than the thickness of their gate oxide, to avoid decreasing their switching speed, or even to increase it.
This faster gate oxide thickness decrease results in increasing the average electric field crossing a gate oxide. This causes “degradations” of the transistors along their use and a decrease in their switching speed. Such physical degradations correspond to an increase in the equivalent drain-source resistance of the transistors and a decrease in their switching speed.
Accordingly, a fast gate oxide thickness decrease, to have high switching speeds, results in reliability problems and variations in the electric characteristics of the transistors along their use.
Such variations are particularly disturbing for certain types of circuits. For the latter, it is then necessary to provide transistors exhibiting thicker gate oxides, to the detriment of their switching speed.